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LTC3557/LTC3557-1 1 35571fc typical application features applications description usb power manager with li-ion charger and three step-down regulators the ltc ? 3557/LTC3557-1 is a highly integrated power management and battery charger ic for single cell li-ion/ polymer battery applications. it includes a powerpath tm manager with automatic load prioritization, a battery charger, an ideal diode and numerous internal protection features. designed speci? cally for usb applications, the LTC3557/LTC3557-1 power manager automatically limits input current to a maximum of either 100ma or 500ma for usb applications or 1a for wall adapter powered applications. battery charge current is automatically reduced such that the sum of the load current and the charge current does not exceed the programmed input current limit. the LTC3557/LTC3557-1 also includes three adjustable synchronous step-down switching regulators and a high voltage buck regulator output controller with bat-track that allows ef? cient charging from supplies as high as 38v. the LTC3557/LTC3557-1 is available in a low pro? le 4mm 4mm 0.75mm 28-pin qfn package. seamless transition between input power sources: li-ion battery, usb, 5v wall adapter or high voltage buck regulator with bat-track tm 200m internal ideal diode plus optional external ideal diode controller provides low loss power path when input current is limited or unavailable triple adjustable high ef? ciency step-down switching regulators (600ma, 400ma, 400ma i out ) pin selectable burst mode ? operation full featured li-ion/polymer battery charger 1.5a maximum charge current with thermal limiting battery float voltage: 4.2v (LTC3557) 4.1v (LTC3557-1) low pro? le 4mm 4mm 28-pin qfn package hdd-based mp3 players pda, pmp , pnd/gps usb-based handheld products + 100ma/500ma 1000ma hv supply 8v to 38v (transients to 60v) usb or 5v adapter charge rst cc/cv charger always on ldo LTC3557/LTC3557-1 triple high efficiency step-down switching regulators high voltage buck dc/dc 0v 3.3v/25ma single cell li-ion v out 0.8v to 3.6v/600ma 0.8v to 3.6v/400ma 0.8v to 3.6v/400ma ntc 35571 ta01a , lt, ltc, ltm and burst mode are registered trademarks of linear technology corporation. bat-track and powerpath are trademarks of linear technology corporation. all other trademarks are the property of their respective owners. protected b y u.s. patents , includin g 6522118 , 6700364. other p atents p endin g . i load (ma) 0 600 500 400 300 200 100 0 C100 300 500 35571 ta01b 100 200 400 600 current (ma) i load i in i bat (charging) i bat (discharging) wall = 0v r prog = 2k r clprog = 2k input and battery current vs load current
LTC3557/LTC3557-1 2 35571fc power manager electrical characteristics absolute maximum ratings v bus , v out , v in1 , v in2 t < 1ms and duty cycle < 1% .................. ?0.3v to 7v steady state ............................................. ?0.3v to 6v bat, ntc, chrg all c debb2brst2 enen2en t llprg cc bs t bat 2a s a s2 s a rst2 chrg acpr a clprg prg 2a t c atr cc str c2c n sbl paraeter cndtns n tp a nts ps bs s bsl tcn ll ll ll a a a bs c lls a a clprg r bs cclprg pc aa clprg clprgscl 2 2 l bs l rt t 2 2 2 2 2 2 tpe 2 pacage 2leads 4mm) plastic qfn 10 11 12 13 14 ilim0 ilim1 wall ldo3v3 sw1 v in1 fb1 gate prog ntc v ntc sw3 v in2 sw2 chrg clprg c acpr bs t bat de en en2 en b b2 rst2 2 2 2 22 t a c a c epsedpadpn2sgndstbeslderedtpcb t t a 2c bs bat llallenen2enr prg 2r clprg 2 pncngratn rdernratn leadreensh tapeandreel partarng pacagedescrptn teperatrerange ltcepb ltcetrpb 2lpn cc ltcepb ltcetrpb 2lpn cc cltc cltc
LTC3557/LTC3557-1 3 35571fc power manager electrical characteristics the denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v bus = 5v, v bat = 3.8v, ilim0 = ilim1 = 5v, wall = en1 = en2 = en3 = 0v, r prog = 2k, r clprog = 2.1k. symbol parameter conditions min typ max units v duvlo v bus to v out differential undervoltage lockout rising threshold falling threshold 50 ? 50 100 mv mv r on_lim input current limit power fet on-resistance (between v bus and v out ) 0.2 battery charger v float v bat regulated output voltage LTC3557 LTC3557, 0c t a 85c LTC3557-1 LTC3557-1, 0c t a 85c 4.179 4.165 4.079 4.065 4.200 4.200 4.100 4.100 4.221 4.235 4.121 4.135 v v v v i chg constant current mode charge current r prog = 1k, input current limit = 2a r prog = 2k, input current limit = 1a r prog = 5k, input current limit = 400ma 950 465 180 1000 500 200 1050 535 220 ma ma ma i bat battery drain current v bus > v uvlo , charger off, i out = 0a v bus = 0v, i out = 0a (ideal diode mode) 6 55 27 100 a a v prog v prog(trkl) prog pin servo voltage prog pin servo voltage in trickle charge bat < v trkl 1.000 0.100 v v h prog ratio of i bat to prog pin current 1000 ma/ma i trkl trickle charge current bat < v trkl 40 50 60 ma v trkl trickle charge rising threshold trickle charge falling threshold bat rising bat falling 2.5 2.85 2.75 3.0 v v v rechrg recharge battery threshold voltage threshold voltage relative to v float ? 75 ? 100 ? 115 mv t term safety timer termination period timer starts when bat = v float C 50mv 3.2 4 4.8 hour t badbat bad battery termination time bat < v trkl 0.4 0.5 0.6 hour h c/10 end-of-charge indication current ratio (note 6) 0.085 0.1 0.115 ma/ma r on(chg) battery charger power fet on-resistance (between v out and bat) 200 m t lim junction temperature in constant temperature mode 110 c ntc v cold cold temperature fault threshold voltage rising ntc voltage hysteresis 75 76 1.3 77 %v vntc %v vntc v hot hot temperature fault threshold voltage falling ntc voltage hysteresis 34 35 1.3 36 %v vntc %v vntc v dis ntc disable threshold voltage falling ntc voltage hysteresis 1.2 1.7 50 2.2 %v vntc mv i ntc ntc leakage current ntc = v bus = 5v ? 50 50 na ideal diode v fwd forward voltage detection i out = 10ma 5 15 25 mv r dropout diode on-resistance, dropout i out = 1a 200 m i max diode current limit (note 7) 3.6 a always on 3.3v supply v ldo3v3 regulated output voltage 0ma < i ldo3v3 < 25ma 3.1 3.3 3.5 v r ol(ldo3v3) open-loop output resistance bat = 3.0v, v bus = 0v 24 r cl(ldo3v3) closed-loop output resistance 3.2
LTC3557/LTC3557-1 4 35571fc power manager electrical characteristics the denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v bus = 5v, v bat = 3.8v, ilim0 = ilim1 = 5v, wall = en1 = en2 = en3 = 0v, r prog = 2k, r clprog = 2.1k. symbol parameter conditions min typ max units wall adapter v acpr acpr pin output high voltage acpr pin output low voltage i acpr = 1ma i acpr = 1ma v out ? 0.3 v out 0 0.3 v v v w absolute wall input threshold voltage wall rising wall falling 3.1 4.3 3.2 4.45 v v v w differential wall input threshold voltage wall ? bat falling wall ? bat rising 025 75 150 mv mv i qwall wall operating quiescent current i wall + i vout , i bat = 0ma, wall = v out = 5v 440 a logic (i lim0 , i lim1 and chrg ) v il input low voltage ilim0, ilim1 0.4 v v ih input high voltage ilim0, ilim1 1.2 v i pd static pull-down current ilim0, ilim1; v pin = 1v 2 a v chrg chrg pin output low voltage i chrg = 10ma 0.15 0.4 v i chrg chrg pin input current bat = 4.5v, chrg = 5v 0 1 a switching regulator electrical characteristics the denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v out = v in1 = v in2 = 3.8v, mode = en1 = en2 = en3 = 0v. symbol parameter conditions min typ max units step-down switching regulators 1, 2 and 3 v in1 , v in2 input supply voltage (note 9) 2.7 5.5 v v out uvl0 v out falling v out rising v in1 and v in2 connected to v out through low impedance. switching regulators are disabled below v out uvlo 2.5 2.7 2.8 2.9 v v f osc oscillator frequency 1.91 2.25 2.59 mhz v il input low voltage mode, en1, en2, en3 0.4 v v ih input high voltage mode, en1, en2, en3 1.2 v i pd static pull-down current mode, en1, en2, en3 (v pin = 1v) 1 a step-down switching regulator 1 i vin1 pulse-skip mode input current (note 10) i out = 0, en1 = 3.8v, mode = 0v 220 a burst mode input current (note 10) i out = 0, en1 = mode = 3.8v 35 50 a shutdown input current i out = 0, en1 = 0v, fb1 = 0v 0.01 1 a i lim1 peak pmos current limit en1 = 3.8v, mode = 0v or 3.8v (note 7) 900 1200 1500 ma v fb1 feedback voltage en1 = 3.8v, mode = 0v en1 = mode = 3.8v 0.78 0.78 0.8 0.8 0.82 0.824 v v i fb1 fb1 input current (note 10) en1 = 3.8v ? 0.05 0.05 a d1 maximum duty cycle fb1 = 0v, en1 = 3.8v 100 % r p1 r ds(on) of pmos en1 = 3.8v 0.3 r n1 r ds(on) of nmos en1 = 3.8v 0.4 r sw1(pd) sw1 pull-down in shutdown en1 = 0v 10 k
LTC3557/LTC3557-1 5 35571fc switching regulator electrical characteristics the denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v out = v in1 = v in2 = 3.8v, mode = en1 = en2 = en3 = 0v. symbol parameter conditions min typ max units step-down switching regulator 2 i vin2 pulse-skip mode input current (note 10) i out = 0, en2 = 3.8v, mode = 0v 220 a burst mode input current (note 10) i out = 0, en2 = mode = 3.8v 35 50 a shutdown input current i out = 0, en2 = 0v, fb2 = 0v 0.01 1 a i lim2 peak pmos current limit en2 = 3.8v, mode = 0v or 3.8v (note 7) 600 800 1000 ma v fb2 feedback voltage en2 = 3.8v, mode = 0v en2 = mode = 3.8v 0.78 0.78 0.8 0.8 0.82 0.824 v v i fb2 fb2 input current (note 10) en2 = 3.8v ? 0.05 0.05 a d2 maximum duty cycle fb2 = 0v, en2 = 3.8v 100 % r p2 r ds(on) of pmos en2 = 3.8v 0.6 r n2 r ds(0n) of nmos en2 = 3.8v 0.6 r sw2(pd) sw2 pull-down in shutdown en2 = 0v 10 k v rst2 power-on rst2 pin output low voltage i rst2 = 1ma, fb2 = 0v, en2 = 3.8v 0.1 0.35 v i rst2 power-on rst2 pin input current (note 10) v rst2 = 5.5v, en2 = 3.8v 1 a v th( rst2 ) power-on rst2 pin threshold (note 8) ? 8 % t rst2 power-on rst2 pin delay from rst2 threshold to rst2 hi-z 230 ms step-down switching regulator 3 i vin2 pulse-skip mode input current (note 10) i out = 0, en3 = 3.8v, mode = 0v 220 a burst mode input current (note 10) i out = 0, en3 = mode = 3.8v 35 50 a shutdown input current i out = 0, en3 = 0v, fb3 = 0v 0.01 1 a i lim3 peak pmos current limt en3 = 3.8v, mode = 0v or 3.8v (note 7) 600 800 1000 ma v fb3 feedback voltage en3 = 3.8v, mode = 0v en3 = mode = 3.8v 0.78 0.78 0.8 0.8 0.82 0.824 v v i fb3 fb3 input current (note 10) en3 = 3.8v ? 0.05 0.05 a d3 maximum duty cycle fb3 = 0v, en3 = 3.8v 100 % r p3 r ds(on) of pmos en3 = 3.8v 0.6 r n3 r ds(on) of nmos en3 = 3.8v 0.6 r sw3(pd) sw3 pull-down in shutdown en3 = 0v 10 k note 1. stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2. the LTC3557/LTC3557-1 is guaranteed to meet performance speci? cations from 0c to 85c. speci? cations over the ? 40c to 85c operating temperature range are assured by design, characterization and correlation with statistical process controls. note 3. this ic includes overtemperature protection that is intended to protect the device during momentary overload conditions. junction temperatures will exceed 110c when overtemperature protection is active. continuous operation above the speci? ed maximum operating junction temperature may result in device degradation or failure. note 4. v cc is the greater of v bus , v out or bat. note 5. total input current is the sum of quiescent current, i busq , and measured current given by v clprog /r clprog ? (h clprog + 1) note 6. h c/10 is expressed as a fraction of measured full charge current with indicated prog resistor. note 7. the current limit features of this part are intended to protect the ic from short term or intermittent fault conditions. continuous operation above the maximum speci? ed pin current rating may result in device degradation or failure. note 8. rst2 threshold is expressed as a percentage difference from the fb2 regulation voltage. the threshold is measured for fb2 rising. note 9. v out not in uvlo. note 10. fb high, not switching.
LTC3557/LTC3557-1 6 35571fc typical performance characteristics input supply current vs temperature input supply current vs temperature (suspend mode) battery drain current vs temperature input current limit vs temperature input r on vs temperature charge current vs temperature (thermal regulation) battery current and voltage vs time (LTC3557) v float load regulation battery regulation (float) voltage vs temperature t a = 25c unless otherwise speci? ed temperature (c) C50 i vbus (ma) 0.7 25 35571 g01 0.4 0.2 C25 0 50 0.1 0 0.8 0.6 0.5 0.3 75 100 125 v bus = 5v 1x mode temperature (c) C50 C25 0 i vbus (ma) 0.04 0.10 0 50 75 35571 g02 0.02 0.08 0.06 25 100 125 v bus = 5v temperature (c) C50 0 i bat (ma) 0.02 0.06 0.08 0.10 0.20 0.14 0 50 75 35571 g03 0.04 0.16 0.18 0.12 C25 25 100 125 v bat = 3.8v mode = 3.8v 3 bucks enabled n0 bucks enabled 2 bucks enabled 1 buck enabled temperature (c) C50 i vbus (ma) 400 1000 1100 1200 0 50 75 35571 g04 200 100 800 600 300 900 0 700 500 C25 25 100 125 v bus = 5v r clprog = 2.1k 10x mode 5x mode 1x mode temperature (c) C50 0 r on (m) 100 140 160 180 300 240 0 50 75 35571 g05 120 260 280 220 C25 25 100 125 i out = 400ma v bus = 4.5v v bus = 5.5v v bus = 5v temperature (c) C50 i bat (ma) 400 500 600 25 75 35571 g06 300 200 C25 0 50 100 125 100 0 v bus = 5v 10x mode r prog = 2k time (hour) 0 0 i bat (ma) v bat and v chrg (v) 100 200 300 400 600 1 234 35571 g07 56 500 0 1 2 3 4 6 v bat i bat c/10 5 1450mahr cell v bus = 5v r prog = 2k r clprog = 2k chrg safety timer termination i bat (ma) 0 v float (v) 4.12 4.14 4.16 600 1000 35571 g08 4.10 4.08 4.06 200 400 800 4.18 4.20 4.22 v bus = 5v 10x mode LTC3557 LTC3557-1 temperature (c) C50 v float (v) 4.06 4.10 4.12 4.14 4.22 4.18 0 50 75 35571 g09 4.08 4.20 4.16 C25 25 100 125 i bat = 2ma LTC3557 LTC3557-1
LTC3557/LTC3557-1 7 35571fc typical performance characteristics i bat vs v bat input disconnect waveform forward voltage vs ideal diode current (no external fet) forward voltage vs ideal diode current (with si2333ds external fet) t a = 25c unless otherwise speci? ed input connect waveform switching from 1x to 5x mode wall connect waveform wall disconnect waveform switching from suspend mode to 5x mode v bat (v) 2.0 0 i bat (ma) 100 200 300 400 600 2.4 2.8 3.2 3.6 35571 g10 4.0 4.4 500 v bus = 5v 10x mode r prog = 2k r clprog = 2k i bat (a) 0 0 v fwd (v) 0.05 0.10 0.15 0.20 0.25 0.2 0.4 0.6 0.8 35571 g11 1.0 1.2 v bat = 3.2v v bus = 0v t a = 25c v bat = 4.2v v bat = 3.6v i bat (a) 0 v fwd (mv) 15 20 25 0.6 1.0 35571 g12 10 5 0 0.2 0.4 0.8 30 35 40 v bat = 3.8v v bus = 0v t a = 25c v bus 5v/div v out 5v/div i bus 0.5a/div i bat 0.5a/div v bat = 3.75v i out = 100ma r clprog = 2k r prog = 2k 1ms/div 35571 g25 v bus 5v/div v out 5v/div i bus 0.5a/div i bat 0.5a/div v bat = 3.75v i out = 100ma r clprog = 2k r prog = 2k 1ms/div 35571 g26 ilim0/ilim1 5v/div i bus 0.5a/div i bat 0.5a/div v bat = 3.75v i out = 50ma r clprog = 2k r prog = 2k 1ms/div 35571 g27 ilim0 5v/div v out 5v/div i bus 0.5a/div i bat 0.5a/div v bat = 3.75v i out = 100ma r clprog = 2k r prog = 2k ilim1 = 5v 100s/div 35571 g28 wall 5v/div v out 5v/div i wall 0.5a/div i bat 0.5a/div v bat = 3.75v i out = 100ma r prog = 2k 1ms/div 35571 g29 wall 5v/div v out 5v/div i wall 0.5a/div i bat 0.5a/div v bat = 3.75v i out = 100ma r prog = 2k 1ms/div 35571 g30
LTC3557/LTC3557-1 8 35571fc oscillator frequency vs temperature step-down switching regulator 1 3.3v output ef? ciency vs i out1 step-down switching regulator output transient (mode = 1) step-down switching regulator output transient (mode = 0) step-down switching regulator switch impedance vs temperature typical performance characteristics t a = 25c unless otherwise speci? ed step-down switching regulator pulse skip supply current vs v inx step-down switching regulator short-circuit current vs temperature temperature (c) C50 1.5 f osc (mhz) 1.6 1.8 1.9 2.0 2.5 2.2 0 50 75 35571 g13 1.7 2.3 2.4 2.1 C25 25 100 125 v in = 5v v in = 3.8v v in = 2.7v v in = 2.9v i out1 (ma) 0.01 40 efficiency (%) 50 60 70 80 0.1 1 10 100 100 0 35571 g14 30 20 10 0 90 100 v in1 = 3.8v v in1 = 5v burst mode operation pulse skip v out1 = 3.3v i out2 (ma) 0.01 40 efficiency (%) 50 60 70 80 0.1 1 10 100 100 0 35571 g15 30 20 10 0 90 100 v in2 = 3.8v v in2 = 5v burst mode operation pulse skip v out2 = 1.2v i out3 (ma) 0.01 40 efficiency (%) 50 60 70 80 0.1 1 10 100 100 0 35571 g16 30 20 10 0 90 100 v in3 = 3.8v v in3 = 5v burst mode operation pulse skip v out3 = 1.8v v inx (v) 2.5 100 i in (a) 150 200 250 300 350 110c 75c 25c C45c 400 3.0 3.5 4.0 4.5 35571 g17 5.0 v outx = 1.2v i outx = 0ma temperature (c) C50 short-circuit current (ma) 1100 25 35571 g18 800 600 C25 0 50 500 400 1200 1000 900 700 75 100 125 600ma buck 400ma buck v out2 50mv/div (ac) v out3 50mv/div (ac) i out2 300ma 5ma 35571 g1 50s/div v out2 = 1.2v v out3 = 1.8v i out3 = 16ma v out2 50mv/div (ac) v out3 50mv/div (ac) i out2 300ma 5ma 35571 g2 50s/div v out2 = 1.2v v out3 = 1.8v i out3 = 100ma temperature (c) C50 0 switch impedance () 0.1 0.3 0.4 0.5 50 0.9 35571 g21 0.2 0 C25 75 100 25 12 5 0.6 0.7 0.8 600ma nmos 600ma pmos 400ma pmos 400ma nmos v inx = 3.2v step-down switching regulator 2 1.2v output ef? ciency vs i out2 step-down switching regulator 3 1.8v output ef? ciency vs i out3
LTC3557/LTC3557-1 9 35571fc pin functions typical performance characteristics t a = 25c unless otherwise speci? ed 400ma step-down switching regulator feedback voltage vs output current step-down switching regulator start-up waveform ilim0, ilim1 (pins 1, 2): input current control pins. ilim0 and ilim1 control the input current limit. see table 1. both pins are pulled low by a weak current sink. wall (pin 3): wall adapter present input. pulling this pin above 4.3v will disconnect the power path from v bus to v out . the acpr pin will also be pulled low to indicate that a wall adapter has been detected. ldo3v3 (pin 4): always on 3.3v ldo output. the ldo3v3 pin provides a regulated, always-on 3.3v supply voltage. this pin gets its power from v out . it may be used for light loads such as a real-time clock or housekeeping microprocessor. a 1f capacitor is required from ldo3v3 to ground if it will be called upon to deliver current. if the ldo3v3 output is not used it should be disabled by connecting it to v out . sw1 (pin 5): power transmission (switch) pin for step-down switching regulator 1. v in1 (pin 6): power input for step-down switching regulator 1. this pin will generally be connected to v out . fb1 (pin 7): feedback input for step-down switching regulator 1. this pin servos to a ? xed voltage of 0.8v when the control loop is complete. mode (pin 8): low power mode enable. when this pin is pulled high, the three step-down switching regulators are set to low power burst mode operation. en1 (pin 9): logic input enables step-down switching regulator 1. en2 (pin 10): logic input enables step-down switching regulator 2. en3 (pin 11): logic input enables step-down switching regulator 3. fb3 (pin 12): feedback input for step-down switching regulator 3. this pin servos to a ? xed voltage of 0.8v when the control loop is complete. fb2 (pin 13): feedback input for step-down switching regulator 2. this pin servos to a ? xed voltage of 0.8v when the control loop is complete. rst2 (pin 14): this is an open-drain output which indicates that step-down switching regulator 2 has settled to its ? nal value. it can be used as a power on reset for the primary microprocessor or to enable the other buck regulators for supply sequencing. sw2 (pin 15): power transmission (switch) pin for step-down switching regulator 2. 600ma step-down switching regulator feedback voltage vs output current output current (ma) 0.78 feedback (v) 0.84 0.85 0.77 0.76 0.83 0.80 0.82 0.81 0.79 0.1 10 100 1000 35571 g22 0.75 1 3.8v 5v burst mode operation pulse skip output current (ma) 0.78 feedback (v) 0.84 0.85 0.77 0.76 0.83 0.80 0.82 0.81 0.79 0.1 10 100 1000 35571 g23 0.75 1 3.8v 5v burst mode operation pulse skip v out2 50mv/div(ac) v out1 1v/div i l1 200ma/div 0v en1 0ma 35571 g2 4 100s/div v out2 = 1.2v i out2 = 50ma mode = 1 r out1 = 8
LTC3557/LTC3557-1 10 35571fc pin functions v in2 (pin 16): power input for step-down switching regu- lators 2 and 3. this pin will generally be connected to v out . sw3 (pin 17): power transmission (switch) pin for step-down switching regulator 3. v ntc (pin 18): output bias voltage for ntc. a resistor from this pin to the ntc pin will bias the ntc thermistor. ntc (pin 19): the ntc pin connects to a batterys thermistor to determine if the battery is too hot or too cold to charge. if the batterys temperature is out of range, charging is paused until it drops back into range. a low drift bias resistor is required from v ntc to ntc and a thermistor is required from ntc to ground. if the ntc function is not desired, the ntc pin should be grounded. prog (pin 20): charge current program and charge current monitor pin. connecting a resistor from prog to ground programs the charge current: i chg (a) = 1000v r prog if suf? cient input power is available in constant current mode, this pin servos to 1v. the voltage on this pin always represents the actual charge current. gate (pin 21): ideal diode gate connection. this pin controls the gate of an optional external p-channel mosfet transistor used to supplement the internal ideal diode. the source of the p-channel mosfet should be connected to v out and the drain should be connected to bat. it is important to maintain high impedance on this pin and minimize all leakage paths. bat (pin 22): single cell li-ion battery pin. depending on available power and load, a li-ion battery on bat will either deliver system power to v out through the ideal diode or be charged from the battery charger. v out (pin 23): output voltage of the powerpath controller and input voltage of the battery charger. the majority of the portable product should be powered from v out . the LTC3557/LTC3557-1 will partition the available power between the external load on v out and the internal battery charger. priority is given to the external load and any extra power is used to charge the battery. an ideal diode from bat to v out ensures that v out is powered even if the load exceeds the allotted input current from v bus or if the v bus power source is removed. v out should be bypassed with a low impedance multilayer ceramic capacitor. the total capacitance on v out should maintain a minimum of 5f over operating voltage and temperature. v bus (pin 24): usb input voltage. v bus will usually be connected to the usb port of a computer or a dc output wall adapter. v bus should be bypassed with a low impedance multilayer ceramic capacitor. acpr (pin 25): wall adapter present output (active low). a low on this pin indicates that the wall adapter input comparator has had its input pulled above its input threshold (typically 4.3v). this pin can be used to drive the gate of an external p-channel mosfet to provide power to v out from a power source other than a usb port. v c (pin 26): high voltage buck regulator control pin. this pin can be used to drive the v c pin of an approved external high voltage buck switching regulator. an external p-channel mosfet is required to provide power to v out with its gate tied to the acpr pin. the v c pin is designed to work with the lt ? 3480, lt3481 and lt3505. clprog (pin 27): input current program and input current monitor pin. a resistor from clprog to ground determines the upper limit of the current drawn from the v bus pin (i.e., the input current limit). a precise fraction of the input current, h clprog , is sent to the clprog pin. the input powerpath delivers current until the clprog pin reaches 2.0v (10x mode), 1.0v (5x mode) or 0.2v (1x mode). therefore, the current drawn from v bus will be limited to an amount given by h clprog and r clprog . in usb applications the resistor r clprog should be set to no less than 2.1k. chrg (pin 28): open-drain charge status output. the chrg pin indicates the status of the battery charger. four possible states are represented by chrg : charging, not charging (i.e., ? oat charge current less than 1/10th programmed charge current), unresponsive battery (i.e., its voltage remains below 2.8v after 1/2 hour of charging) and battery temperature out of range. chrg requires a pull-up resistor and/or led to provide indication. exposed pad (pin 29): ground. the exposed package pad is ground and must be soldered to the pc board for proper functionality and for maximum heat transfer.
LTC3557/LTC3557-1 11 35571fc block diagram ntc 19 v ntc 15mv 18 v bus wall clprog 27 6 5 7 osc ref 600ma, 2.25mhz buck regulator v in1 3.3v ldo sw1 fb1 en mode 4 ldo3v3 20 prog 22 bat 21 gate 23 v out 16 15 13 osc 400ma, 2.25mhz buck regulator v in2 sw2 fb2 en mode 17 12 osc rst2 400ma, 2.25mhz buck regulator sw3 fb3 35571 bd en mode en logic battery temp monitor chrg 28 charge status ilim logic cc/cv charger wall detect input current limit 14 gnd 29 mode 8 en3 11 en2 10 en1 9 2 ilim0 ilim1 1 24 3 v c 26 acpr 25 v c control + C + C ideal diode
LTC3557/LTC3557-1 12 35571fc operation introduction the LTC3557/LTC3557-1 is a highly integrated power management ic that includes a powerpath controller, battery charger, an ideal diode, an always-on ldo, three synchronous step-down switching regulators as well as a buck regulator v c controller. designed speci? cally for usb applications, the powerpath controller incorporates a precision input current limit which communicates with the battery charger to ensure that input current never violates the usb speci? cations. the ideal diode from bat to v out guarantees that ample power is always available to v out even if there is insuf? cient or absent power at v bus . the LTC3557/LTC3557-1 also has the ability to receive power from a wall adapter or other non-current-limited power source. such a power supply can be connected to the v out pin of the LTC3557/LTC3557-1 through an external device such as a power schottky or fet as shown in figure 1. the LTC3557/LTC3557-1 has the unique ability to use the output, which is powered by an external supply, to charge the battery while providing power to the load. a comparator on the wall pin is con? gured to detect the presence of the wall adapter and shut off the connection to the usb. this prevents reverse conduction from v out to v bus when a wall adapter is present. the LTC3557/LTC3557-1 provides a v c output pin which can be used to drive the v c pin of an external high voltage buck switching regulator such as the lt3480, lt3481, or lt3505 to provide power to the v out pin. the v c control circuitry adjusts the regulation point of the switching regulator to a small voltage above the bat pin voltage. this control method provides a high input voltage, high ef? ciency battery charger and powerpath function. an always on ldo provides a regulated 3.3v from v out . this ldo will be on at all times and can be used to supply up to 25ma. figure 1. simpli? ed powerpath block diagram + C + C + C + C 4.3v (rising) 3.2v (falling) 75mv (rising) 25mv (falling) enable usb current limit constant current constant voltage battery charger wall from ac adapter (or high voltage buck output) 3 v bus from usb 24 21 + C 15mv gate bat 35571 f01 li-ion optional external ideal diode pmos bat ideal diode 22 23 v out v out v c optional control for high voltage buck regs lt3480, lt3481 or lt3505 25 acpr 26 + system load
LTC3557/LTC3557-1 13 35571fc operation the LTC3557/LTC3557-1 includes three 2.25mhz constant frequency current mode step-down switching regulators providing 400ma, 400ma and 600ma each. all step- down switching regulators can be programmed for a minimum output voltage of 0.8v and can be used to power a microcontroller core, microcontroller i/o, memory or other logic circuitry. all step-down switching regulators support 100% duty cycle operation and are capable of operating in burst mode operation for highest ef? ciencies at light loads (burst mode operation is pin selectable). no external compensation components are required for the switching regulators. usb powerpath controller the input current limit and charge control circuits of the LTC3557/LTC3557-1 are designed to limit input current as well as control battery charge current as a function of i vout . v out drives the combination of the external load, the three step-down switching regulators, always on 3.3v ldo and the battery charger. if the combined load does not exceed the programmed input current limit, v out will be connected to v bus through an internal 200m p-channel mosfet. if the combined load at v out exceeds the programmed input current limit, the battery charger will reduce its charge current by the amount necessary to enable the external load to be satis? ed while maintaining the programmed input current. even if the battery charge current is set to exceed the allowable usb current, the average input current usb speci? cation will not be violated. furthermore, load current at v out will always be prioritized and only excess available current will be used to charge the battery. the current out of the clprog pin is a fraction (1/h clprog ) of the v bus current. when a programming resistor is con- nected from clprog to gnd, the voltage on clprog represents the input current: i vbus = i busq + v clprog r clprog ?h clprog where i busq and h clprog are given in the electrical characteristics. the input current limit is programmed by the ilim0 and ilim1 pins. the LTC3557/LTC3557-1 can be con? gured to limit input current to one of several possible settings as well as be deactivated (usb suspend). the input current limit will be set by the appropriate servo voltage and the resistor on clprog according to the following expression: i vbus = i busq + 0.2v r clprog ?h clprog 1x mode () i vbus = i busq + 1v r clprog ?h clprog 5x mode () i vbus = i busq + 2v r clprog ?h clprog 10x mode () under worst-case conditions, the usb speci? cation will not be violated with an r clprog resistor of greater than 2.1k. table 1 shows the available settings for the ilim0 and ilim1 pins: table 1: controlled input current limit ilim1 ilim0 i bus(lim) 0 0 100ma (1x) 0 1 1a (10x) 1 0 suspend 1 1 500ma (5x) notice that when ilim0 is high and ilim1 is low, the input current limit is set to a higher current limit for increased charging and current availability at v out . this mode is typically used when there is power available from a wall adapter. ideal diode from bat to v out the LTC3557/LTC3557-1 has an internal ideal diode as well as a controller for an optional external ideal diode. both the internal and the external ideal diodes respond quickly whenever v out drops below bat. if the load increases beyond the input current limit, ad- ditional current will be pulled from the battery via the ideal diodes. furthermore, if power to v bus (usb) or v out (external wall power or high voltage regulator) is removed, then all of the application power will be provided
LTC3557/LTC3557-1 14 35571fc by the battery via the ideal diodes. the ideal diodes are fast enough to keep v out from dropping with just the recommended output capacitor. the ideal diode consists of a precision ampli? er that enables an on-chip p-channel mosfet whenever the voltage at v out is approximately 15mv (v fwd ) below the voltage at bat. the resistance of the internal ideal diode is approximately 200m. if this is suf? cient for the application, then no external components are necessary. however, if more conductance is needed, an external p-channel mosfet can be added from bat to v out . the gate pin of the LTC3557/LTC3557-1 drives the gate of the external p-channel mosfet for automatic ideal diode control. the source of the mosfet should be connected to v out and the drain should be connected to bat. capable of driving a 1nf load, the gate pin can control an external p-channel mosfet having extremely low on-resistance. using the wall pin to detect the presence of an external power source the wall input pin can be used to identify the presence of an external power source (particularly one that is not subject to a ? xed current limit like the usb v bus input). typically, such a power supply would be a 5v wall adapter output or the low voltage output of a high voltage buck regulator (speci? cally, lt3480, lt3481 or lt3505). when the wall adapter output (or buck regulator output) is con- nected directly to the wall pin, and the voltage exceeds the wall pin threshold, the usb power path (from v bus to v out ) will be disconnected. furthermore, the acpr pin will be pulled low. in order for the presence of an external power supply to be acknowledged, both of the following conditions must be satis? ed: 1. the wall pin voltage must exceed approximately 4.3v. 2. the wall pin voltage must exceed 75mv above the bat pin voltage. the input power path (between v bus and v out ) is re-enabled and the acpr pin is pulled high when either of the following conditions is met: 1. the wall pin voltage falls to within 25mv of the bat pin voltage. 2. the wall pin voltage falls below 3.2v. each of these thresholds is suitably ? ltered in time to prevent transient glitches on the wall pin from falsely triggering an event. see the applications information section for an explanation of high voltage buck regulator control using the v c pin. suspend mode when ilim0 is pulled low and ilim1 is pulled high the LTC3557/LTC3557-1 enters suspend mode to comply with the usb speci? cation. in this mode, the power path between v bus and v out is put in a high impedance state to reduce the v bus input current to 50a. if no other power source is available to drive wall and v out , the system load connected to v out is supplied through the ideal diodes connected to bat. if an external power source drives wall and v out such that v out < v bus , the suspend mode v bus input current can be as high as 200a. 3.3v always-on supply the LTC3557/LTC3557-1 includes an ultralow quiescent current low dropout regulator that is always powered. this ldo can be used to provide power to a system pushbutton controller or standby microcontroller. designed to deliver up to 25ma, the always-on ldo requires a 1f mlcc bypass capacitor for compensation. the ldo is powered from v out , and therefore will enter dropout at loads less than 25ma as v out falls near 3.3v. if the ldo3v3 output is not used, it should be disabled by connecting it to v out . v bus undervoltage lockout (uvlo) an internal undervoltage lockout circuit monitors v bus and keeps the input current limit circuitry off until v bus rises above the rising uvlo threshold (3.8v) and at least 50mv above v out . hysteresis on the uvlo turns off the input current limit if v bus drops below 3.7v or 50mv below v out . when this happens, system power at v out will be drawn from the battery via the ideal diode. to minimize the possibility of oscillation in and out of uvlo when using resistive input supplies, the input current limit is reduced as v bus drops below 4.45v typical. operation
LTC3557/LTC3557-1 15 35571fc battery charger the LTC3557/LTC3557-1 includes a constant current/con- stant voltage battery charger with automatic recharge, automatic termination by safety timer, low voltage trickle charging, bad cell detection and thermistor sensor input for out of temperature charge pausing. when a battery charge cycle begins, the battery charger ? rst determines if the battery is deeply discharged. if the battery voltage is below v trkl , typically 2.85v, an automatic trickle charge feature sets the battery charge current to 10% of the programmed value. if the low voltage persists for more than 1/2 hour, the battery charger automatically terminates and indicates via the chrg pin that the battery was unresponsive. once the battery voltage is above 2.85v, the battery charger begins charging in full power constant current mode. the current delivered to the battery will try to reach 1000v/ r prog . depending on available input power and external load conditions, the battery charger may or may not be able to charge at the full programmed rate. the external load will always be prioritized over the battery charge current. the usb current limit programming will always be observed and only additional current will be available to charge the battery. when system loads are light, battery charge current will be maximized. charge termination the battery charger has a built-in safety timer. when the battery voltage approaches the ? oat voltage (4.2v for LTC3557 or 4.1v for LTC3557-1), the charge current begins to decrease as the LTC3557/LTC3557-1 enters constant voltage mode. once the battery charger detects that it has entered constant voltage mode, the four hour safety timer is started. after the safety timer expires, charging of the battery will terminate and no more current will be delivered. automatic recharge after the battery charger terminates, it will remain off drawing only microamperes of current from the battery. if the portable product remains in this state long enough, the battery will eventually self discharge. to ensure that the battery is always topped off, a charge cycle will automati- cally begin when the battery voltage falls below v rechrg (typically 4.1v for the LTC3557 or 4v for LTC3557-1). in the event that the safety timer is running when the battery voltage falls below v rechrg , the timer will reset back to zero. to prevent brief excursions below v rechrg from re- setting the safety timer, the battery voltage must be below v rechrg for more than 1.3ms. the charge cycle and safety timer will also restart if the v bus uvlo cycles low and then high (e.g., v bus , is removed and then replaced). charge current the charge current is programmed using a single resistor from prog to ground. 1/1000th of the battery charge current is delivered to prog which will attempt to servo to 1.000v. thus, the battery charge current will try to reach 1000 times the current in the prog pin. the program resistor and the charge current are calculated using the following equations: r prog = 1000v i chg , i chg = 1000v r prog in either the constant current or constant voltage charging modes, the prog pin voltage will be proportional to the actual charge current delivered to the battery. therefore, the actual charge current can be determined at any time by monitoring the prog pin voltage and using the following equation: i bat = v prog r prog ? 1000 in many cases, the actual battery charge current, i bat , will be lower than i chg due to limited input current available and prioritization with the system load drawn from v out . thermal regulation to prevent thermal damage to the ic or surrounding components, an internal thermal feedback loop will automatically decrease the programmed charge current if the die temperature rises to approximately 110c. thermal regulation protects the LTC3557/LTC3557-1 from excessive temperature due to high power operation operation
LTC3557/LTC3557-1 16 35571fc operation or high ambient thermal conditions and allows the user to push the limits of the power handling capability with a given circuit board design without risk of damaging the LTC3557/LTC3557-1 or external components. the bene? t of the LTC3557/LTC3557-1 thermal regulation loop is that charge current can be set according to actual conditions rather than worst-case conditions with the assurance that the battery charger will automatically reduce the current in worst-case conditions. charge status indication the chrg pin indicates the status of the battery charger. four possible states are represented by chrg which include charging, not charging, unresponsive battery and battery temperature out of range. the signal at the chrg pin can be easily recognized as one of the above four states by either a human or a mi- croprocessor. an open-drain output, the chrg pin can drive an indicator led through a current limiting resistor for human interfacing or simply a pull-up resistor for microprocessor interfacing. to make the chrg pin easily recognized by both humans and microprocessors, the pin is either a dc signal of on for charging, off for not charging, or it is switched at high frequency (35khz) to indicate the two possible faults, unresponsive battery, and battery temperature out of range. when charging begins, chrg is pulled low and remains low for the duration of a normal charge cycle. when charg- ing is complete, i.e., the charger enters constant voltage mode and the charge current has dropped to one-tenth of the programmed value, the chrg pin is released (high impedance). the chrg pin does not respond to the c/10 threshold if the LTC3557/LTC3557-1 is in input current limit. this prevents false end of charge indications due to insuf? cient power available to the battery charger. if a fault occurs, the pin is switched at 35khz. while switching, its duty cycle is modulated between a high and low value at a very low frequency. the low and high duty cycles are disparate enough to make an led appear to be on or off thus giving the appearance of blinking. each of the two faults has its own unique blink rate for human recognition as well as two unique duty cycles for machine recognition. table 2: illustrates the four possible states of the chrg pin when the battery charger is active. table 2: chrg output pin status frequency modulation (blink) frequency duty cycle charging 0hz 0hz (lo-z) 100% i bat < c/10 0hz 0hz (hi-z) 0% ntc fault 35khz 1.5hz at 50% 6.25% or 93.75% bad battery 35khz 6.1hz at 50% 12.5% or 87.5% an ntc fault is represented by a 35khz pulse train whose duty cycle toggles between 6.25% and 93.75% at a 1.5hz rate. a human will easily recognize the 1.5hz rate as a slow blinking which indicates the out-of-range battery temperature while a microprocessor will be able to decode either the 6.25% or 93.75% duty cycles as an ntc fault. if a battery is found to be unresponsive to charging (i.e., its voltage remains below v trkl , typically 2.8v, for 1/2 hour), the chrg pin gives the battery fault indication. for this fault, a human would easily recognize the frantic 6.1hz fast blink of the led while a microprocessor would be able to decode either the 12.5% or 87.5% duty cycles as a bad battery fault. note that the LTC3557/LTC3557-1 is a 3-terminal powerpath product where system load is always prioritized over battery charging. due to excessive system load, there may not be suf? cient power to charge the battery beyond the trickle charge threshold voltage within the bad battery timeout period. in this case, the battery charger will falsely indicate a bad battery. system software may then reduce the load and reset the battery charger to try again. although very improbable, it is possible that a duty cycle reading could be taken at the bright-dim transition (low duty cycle to high duty cycle). when this happens the duty cycle reading will be precisely 50%. if the duty cycle reading is 50%, system software should disqualify it and take a new duty cycle reading.
LTC3557/LTC3557-1 17 35571fc operation ntc thermistor the battery temperature is measured by placing a negative temperature coef? cient (ntc) thermistor close to the bat- tery pack. the ntc circuitry is shown in figure 8. to use this feature connect the ntc thermistor, r ntc , between the ntc pin and ground and a bias resistor, r nom , from v ntc to ntc. r nom should be a 1% resistor with a value equal to the value of the chosen ntc thermistor at 25c (r25). a 100k thermistor is recommended since thermistor current is not measured by the LTC3557/LTC3557-1 and will have to be considered for usb compliance. the LTC3557/LTC3557-1 will pause charging when the resistance of the ntc thermistor drops to 0.54 times the value of r25 or approximately 54k (for a vishay curve 1 thermistor, this corresponds to approximately 40c). if the battery charger is in constant voltage (? oat) mode, the safety timer also pauses until the thermistor indicates a return to a valid temperature. as the temperature drops, the resistance of the ntc thermistor rises. the LTC3557/ LTC3557-1 is also designed to pause charging when the value of the ntc thermistor increases to 3.25 times the value of r25. for a vishay curve 1 thermistor this resistance, 325k, corresponds to approximately 0c. the hot and cold comparators each have approximately 3c of hysteresis to prevent oscillation about the trip point. grounding the ntc pin disables all ntc functionality. general purpose step-down switching regulators the LTC3557/LTC3557-1 includes three 2.25mhz constant frequency current mode step-down switching regulators providing 400ma, 400ma and 600ma each. all step-down switching regulators can be programmed for a minimum output voltage of 0.8v and can be used to power a micro- controller core, microcontroller i/o, memory or other logic circuitry. all step-down switching regulators support 100% duty cycle operation (low dropout mode) when the input voltage drops very close to the output voltage and are also capable of burst mode operation for highest ef? ciencies at light loads (burst mode operation is pin selectable). the step-down switching regulators also include soft-start to limit inrush current when powering on, short-circuit current protection, and switch node slew limiting circuitry to reduce emi radiation. no external compensation components are required for the switching regulators. a single mode pin sets all step-down switching regulators in burst mode or pulse-skip mode operation, while each regulator is enabled individually through their respective enable pins (en1, en2 and en3). it is recommended that the step-down switching regulator input supplies (v in1 and v in2 ) be connected to the system supply pin (v out ). this allows the undervoltage lock out circuit on the v out pin (v out uvlo)to disable the step-down switching regulators when the v out voltage drops below v out uvlo threshold. if driving the step-down switching regulator input supplies from a voltage other than v out the regulators should not be operated outside the speci? ed operating range as operation is not guaranteed beyond this range. step-down switching regulator output voltage programming figure 2 shows the step-down switching regulator application circuit. the full-scale output voltage for each step-down switching regulator is programmed using a resistor divider from the step-down switching regulator output connected to the feedback pins (fb1, fb2 and fb3) such that: v outx = 0.8v ? r1 r2 + 1 ? ? ? ? ? ? typical values for r1 are in the range of 40k to 1m. the capacitor c fb cancels the pole created by feedback resistors and the input capacitance of the fb pin and also helps to improve transient response for output voltages much greater than 0.8v. a variety of capacitor sizes can be used for c fb but a value of 10pf is recommended for most applications. experimentation with capacitor sizes between 2pf and 22pf may yield improved transient response. figure 2. buck converter application circuit pwm control v in 0.8v mn mp en mode swx l fbx gnd c fb c out v outx r1 r2 35571 f02
LTC3557/LTC3557-1 18 35571fc step-down switching regulator rst2 operation the rst2 pin is an open-drain output used to indicate that step-down switching regulator 2 has been enabled and has reached its ? nal voltage. a 230ms delay is included from the time switching regulator 2 reaches 92% of its regulation value to allow a system controller ample time to reset itself. rst2 may be used as a power-on reset to the microprocessor powered by regulator 2 or may be used to enable regulators 1 and/or 3 for supply sequencing. rst2 is an open-drain output and requires a pull-up resistor to the output voltage of regulator 2 or another appropriate power source. step-down switching regulator operating modes the step-down switching regulators include two possible operating modes to meet the noise/power needs of a variety of applications. in pulse-skip mode, an internal latch is set at the start of every cycle, which turns on the main p-channel mosfet switch. during each cycle, a current comparator compares the peak inductor current to the output of an error ampli? er. the output of the current comparator resets the internal latch, which causes the main p-channel mosfet switch to turn off and the n-channel mosfet synchronous recti? er to turn on. the n-channel mosfet synchronous recti? er turns off at the end of the 2.25mhz cycle or if the current through the n-channel mosfet synchronous recti? er drops to zero. using this method of operation, the error ampli? er adjusts the peak inductor current to deliver the required output power. all necessary compensation is internal to the step-down switching regulator requiring only a single ceramic output capacitor for stability. at light loads in pulse-skip mode, the inductor current may reach zero on each pulse which will turn off the n-channel mosfet synchronous recti? er. in this case, the switch node (sw1, sw2 or sw3) goes high impedance and the switch node voltage will ring. this is discontinuous operation, and is normal behavior for a switching regulator. at very light loads in pulse-skip mode, the step-down switching regulators will automatically skip pulses as needed to maintain output regulation. at high duty cycle (v outx > v inx /2) it is possible for the inductor current to reverse at light loads causing the stepped down switching regulator to operate continuously. when operating continuously, regulation and low noise output voltage are maintained, but input operating current will increase to a few milliamps. in burst mode operation, the step-down switching regula- tors automatically switch between ? xed frequency pwm operation and hysteretic control as a function of the load current. at light loads the step-down switching regulators control the inductor current directly and use a hysteretic control loop to minimize both noise and switching losses. while operating in burst mode operation, the output capaci- tor is charged to a voltage slightly higher than the regulation point. the step-down switching regulator then goes into sleep mode, during which the output capacitor provides the load current. in sleep mode, most of the switching regulators circuitry is powered down, helping conserve battery power. when the output voltage drops below a pre-determined value, the step-down switching regulator circuitry is powered on and another burst cycle begins. the sleep time decreases as the load current increases. beyond a certain load current point (about 1/4 rated output load current) the step-down switching regulators will switch to a low noise constant frequency pwm mode of operation, much the same as pulse-skip operation at high loads. for applications that can tolerate some output ripple at low output currents, burst mode operation provides better ef? ciency than pulse-skip at light loads. the step-down switching regulators allow mode transition on-the-? y, providing seamless transition between modes even under load. this allows the user to switch back and forth between modes to reduce output ripple or increase low current ef? ciency as needed. burst mode operation is set by driving the mode pin high, while pulse-skip mode is achieved by driving the mode pin low. step-down switching regulator in shutdown the step-down switching regulators are in shutdown when not enabled for operation. in shutdown all circuitry in the step-down switching regulator is disconnected from the switching regulator input supply leaving only a few nanoamps of leakage current. the step-down switching regulator outputs are individually pulled to ground through a 10k resistor on the switch pin (sw1, sw2 or sw3) when in shutdown. operation
LTC3557/LTC3557-1 19 35571fc step-down switching regulator dropout operation it is possible for a step-down switching regulators input voltage to approach its programmed output voltage (e.g., a battery voltage of 3.4v with a programmed output voltage of 3.3v). when this happens, the pmos switch duty cycle increases until it is turned on continuously at 100%. in this dropout condition, the respective output voltage equals the regulators input voltage minus the voltage drops across the internal p-channel mosfet and the inductor. step-down switching regulator soft-start operation soft-start is accomplished by gradually increasing the peak inductor current for each step-down switching regulator over a 500s period. this allows each output to rise slowly, helping minimize inrush current required to charge up the switching regulator output capacitor. a soft-start cycle occurs whenever a given switching regulator is enabled, or after a fault condition has occurred (thermal shutdown or uvlo). a soft-start cycle is not triggered by changing operating modes. this allows seamless output transition when actively changing between operating modes. step-down switching regulator switching slew rate control the step-down switching regulators contain new patent- pending circuitry to limit the slew rate of the switch node (sw1, sw2 and sw3). this new circuitry is designed to transition the switch node over a period of a couple nano- seconds, signi? cantly reducing radiated emi and conducted supply noise while maintaining high ef? ciency. step-down switching regulator low supply operation an undervoltage lockout (uvlo) circuit on v out shuts down the step-down switching regulators when v out drops below about 2.7v. it is recommended that the step-down switching regulators input supplies be connected to the power path output (v out ). this uvlo prevents the step-down switching regulators from operating at low supply voltages where loss of regulation or other un- desirable operation may occur. if driving the step-down switching regulator input supplies from a voltage other than the v out pin, the regulators should not be operate operation outside the speci? ed operating range as operation is not guaranteed beyond this range. step-down switching regulator inductor selection many different sizes and shapes of inductors are avail- able from numerous manufacturers. choosing the right inductor from such a large selection of devices can be overwhelming, but following a few basic guidelines will make the selection process much simpler. the step-down converters are designed to work with inductors in the range of 2.2h to 10h. for most applications a 4.7h inductor is suggested for step-down switching regulators providing up to 400ma of output current while a 3.3h inductor is suggested for step-down switching regulators providing up to 600ma. larger value inductors reduce ripple current, which improves output ripple voltage. lower value inductors result in higher ripple current and improved transient response time, but will reduce the available output current. to maximize ef? ciency, choose an inductor with a low dc resistance. for a 1.2v output, ef? ciency is reduced about 2% for 100m series resistance at 400ma load current, and about 2% for 300m series resistance at 100ma load current. choose an inductor with a dc current rating at least 1.5 times larger than the maximum load current to ensure that the inductor does not saturate during normal operation. if output short circuit is a possible condition, the inductor should be rated to handle the maximum peak current speci? ed for the step-down converters. different core materials and shapes will change the size/cur- rent and price/current relationship of an inductor. toroid or shielded pot cores in ferrite or permalloy materials are small and dont radiate much energy, but generally cost more than powdered iron core inductors with similar electrical characteristics. inductors that are very thin or have a very small volume typically have much higher core and dcr losses, and will not give the best ef? ciency. the choice of which style inductor to use often depends more on the price vs size, performance, and any radiated emi requirements than on what the step-down switching regulators requires to operate.
LTC3557/LTC3557-1 20 35571fc operation the inductor value also has an effect on burst mode operation. lower inductor values will cause burst mode switching frequency to increase. table 3 shows several inductors that work well with the step-down switching regulators. these inductors offer a good compromise in current rating, dcr and physical size. consult each manufacturer for detailed information on their entire selection of inductors. step-down switching regulator input/output capacitor selection low esr (equivalent series resistance) ceramic capacitors should be used at both step-down switching regulator outputs as well as at each step-down switching regulator input supply. only x5r or x7r ceramic capacitors should be used because they retain their capacitance over wider voltage and temperature ranges than other ceramic types. a 10f output capacitor is suf? cient for the step-down switching regulator outputs. for good transient response and stability the output capacitor for step-down switching regulators should retain at least 4f of capacitance over operating temperature and bias voltage. each switching regulator input supply should be bypassed with a 2.2f capacitor. consult with capacitor manufacturers for detailed information on their selection and speci? cations of ceramic capacitors. many manufacturers now offer very thin (<1mm tall) ceramic capacitors ideal for use in height-restricted designs. table 4 shows a list of several ceramic capacitor manufacturers. table 4. ceramic capacitor manufacturers avx www.avxcorp.com murata www.murata.com taiyo yuden www.t-yuden.com vishay siliconix www.vishay.com tdk www.tdk.com table 3. recommended inductors for step-down switching regulators inductor type l (h) max i dc (a) max dcr () size in mm (l w h) manufacturer de2818c d312c de2812c 4.7 3.3 4.7 3.3 4.7 3.3 1.25 1.45 0.79 0.90 1.2 1.4 0.072 0.053 0.24 0.20 0.13* 0.105* 3.0 2.8 1.8 3.0 2.8 1.8 3.6 3.6 1.2 3.6 3.6 1.2 3.0 2.8 1.2 3.0 2.8 1.2 toko www.toko.com cdrh3d16 cdrh2d11 cls4d09 4.7 3.3 4.7 3.3 4.7 0.9 1.1 0.5 0.6 0.75 0.11 0.085 0.17 0.123 0.19 4.0 4.0 1.8 4.0 4.0 1.8 3.2 3.2 1.2 3.2 3.2 1.2 4.9 4.9 1.0 sumida www.sumida.com sd3118 sd3112 sd12 sd10 4.7 3.3 4.7 3.3 4.7 3.3 4.7 3.3 1.3 1.59 0.8 0.97 1.29 1.42 1.08 1.31 0.162 0.113 0.246 0.165 0.117* 0.104* 0.153* 0.108* 3.1 3.1 1.8 3.1 3.1 1.8 3.1 3.1 1.2 3.1 3.1 1.2 5.2 5.2 1.2 5.2 5.2 1.2 5.2 5.2 1.0 5.2 5.2 1.0 cooper www.cooperet.com lps3015 4.7 3.3 1.1 1.3 0.2 0.13 3.0 3.0 1.5 3.0 3.0 1.5 coil craft www.coilcraft.com *typical dcr
LTC3557/LTC3557-1 21 35571fc applications information external hv buck control through the v c pin the wall, acpr and v c pins can be used in conjunction with an external high voltage buck regulator such as the lt ? 3480, lt3481 or lt3505 to provide power directly to the v out pin through a power p-channel mosfet as shown in figures 3-5 (consult the factory for a complete list of approved high voltage buck regulators). when the wall pin voltage exceeds 4.3v, v c pin control circuitry is enabled and drives the v c pin of the lt3480, lt3481 or lt3505. the v c pin control circuitry is designed so that no compensation components are required on the v c node. the voltage at the v out pin is regulated to the larger of (bat + 300mv) or 3.6v as shown in figures 6 and 7. the feedback network of the high voltage regulator should be set to generate an output voltage higher than 4.4v (be sure to include the output voltage tolerance of the buck regula- tor). the v c control of the LTC3557 overdrives the local v c control of the external high voltage buck. therefore, once the v c control is enabled, the output voltage is set independent of the buck regulator feedback network. v in 2 3 dfls240l 0.47f 22f c out v out up to 2a bat 35571 f03 li-ion si2333ds si2333ds (opt) 6.8h 4 5 6 7 nc nc 10 boost v c 26 3 25 23 21 22 LTC3557 LTC3557-1 wall acpr gate v out bat run/ss 150k 40.2k 68nf 4.7f hv in 8v to 38v (transients to 60v) 499k 100k sw r t 1 bd 8 11 9 fb lt3480 lt3480 high voltage buck circuitry gnd v c + v in 2 3 7 dfls240l 0.47f 22f c out up to 2a v out bat 35571 f04 li-ion si2333ds si2333ds (opt) 6.8h 4 5 6 nc 10 boost v c 26 3 25 23 21 22 LTC3557 LTC3557-1 wall acpr gate v out bat run/ss 150k 60.4k 68nf 4.7f hv in 8v to 34v 549k 200k sw r t bias 1 bd 8 11 9 fb lt3481 lt3481 high voltage buck circuitry gnd v c + figure 3. lt3480 buck control using v c (800khz switching) figure 4. lt3481 buck control using v c (800khz switching)
LTC3557/LTC3557-1 22 35571fc applications information this technique provides a signi? cant ef? ciency advantage over the use of a 5v buck to drive the battery charger. with a simple 5v buck output driving v out , battery charger ef? ciency is approximately: charger = buck ? v bat 5v where buck is the ef? ciency of the high voltage buck regulator and 5v is the output voltage of the buck regulator. with a typical buck ef? ciency of 87% and a typical battery voltage of 3.8v, the total battery charger ef? ciency is approximately 66%. assuming a 1a charge current, this works out to nearly 2w of power dissipation just to charge the battery! with the v c control technique, battery charger ef? ciency is approximately: charger = buck ? v bat 0.3v + v bat with the same assumptions as above, the total battery charger ef? ciency is approximately 81%. this example works out to just 900mw of power dissipation. for applications, component selection and board layout information beyond those listed here please refer to the respective lt3480, lt3481 or lt3505 data sheet. v in r t 1 2 mbrm140 0.1f 10f c out up to 1.2a v out bat 35571 f05 li-ion si2333ds si2333ds (opt) 6.8h 1n4148 3 4 6 boost v c 26 3 25 23 21 22 LTC3557 LTC3557-1 wall acpr gate v out bat shdn 150k 806k bzt52c16t 20k 68nf 1f hv in 8v to 36v 49.9k 10.0k sw 7 5, 9 8 fb lt3505 lt3505 high voltage buck circuitry gnd v c + figure 5. lt3505 buck control using v c (2.2mhz switching with frequency foldback) bat (v) 2.5 v out (v) 3.5 4.0 4.5 35571 f06 3.0 2.5 3 3.5 4 5.0 4.5 i o = 0.0a i o = 0.75a i o = 1.5a bat bat (v) 2.5 v out (v) 3.5 4.0 4.5 35571 f07 3.0 2.5 3 3.5 4 5.0 4.5 i o = 0.0a i o = 0.6a bat figure 6. LTC3557 v out voltage vs battery voltage with the lt3480 figure 7. LTC3557-1v out voltage vs battery voltage with the lt3505
LTC3557/LTC3557-1 23 35571fc alternate ntc thermistors and biasing the LTC3557/LTC3557-1 provides temperature quali? ed charging if a grounded thermistor and a bias resistor are connected to ntc. by using a bias resistor whose value is equal to the room temperature resistance of the thermistor (r25) the upper and lower temperatures are pre-programmed to approximately 40c and 0c, respectively (assuming a vishay curve 1 thermistor). the upper and lower temperature thresholds can be adjusted by either a modi? cation of the bias resistor value or by adding a second adjustment resistor to the circuit. if only the bias resistor is adjusted, then either the upper or the lower threshold can be modi? ed but not both. the other trip point will be determined by the characteristics of the thermistor. using the bias resistor in addition to an adjustment resistor, both the upper and the lower temperature trip points can be independently programmed with the constraint that the difference between the upper and lower temperature thresholds cannot decrease. examples of each technique are given below. ntc thermistors have temperature characteristics which are indicated on resistance-temperature conversion tables. the vishay-dale thermistor nths0603n011-n1003f, used in the following examples, has a nominal value of 100k and follows the vishay curve 1 resistance-temperature characteristic. in the explanation below, the following notation is used. r25 = value of the thermistor at 25c r ntc|cold = value of thermistor at the cold trip point r ntc|hot = value of the thermistor at the hot trip point r cold = ratio of r ntc|cold to r25 r hot = ratio of r ntc|hot to r25 r nom = primary thermistor bias resistor (see figure 8) r1 = optional temperature range adjustment resistor (see figure 9) the trip points for the LTC3557/LTC3557-1s temperature quali? cation are internally programmed at 0.349 ? v vntc for the hot threshold and 0.765 ? v vntc for the cold threshold. therefore, the hot trip point is set when: r ntc|hot r nom + r ntc|hot ?v vntc = 0.349 ? v vntc and the cold trip point is set when: r ntc|cold r nom + r ntc|cold ?v vntc = 0.765 ? v vntc solving these equations for r ntc|cold and r ntc|hot results in the following: r ntc|hot = 0.536 ? r nom and r ntc|cold = 3.25 ? r nom by setting r nom equal to r25, the above equations result in r hot = 0.536 and r cold = 3.25. referencing these ratios to the vishay resistance-temperature curve 1 chart gives a hot trip point of about 40c and a cold trip point of about 0c. the difference between the hot and cold trip points is approximately 40c. by using a bias resistor, r nom , different in value from r25, the hot and cold trip points can be moved in either direction. the temperature span will change somewhat due to the non-linear behavior of the thermistor. the following equations can be used to easily calculate a new value for the bias resistor: r nom = r hot 0.536 ?r25 r nom = r cold 3.25 ?r25 where r hot and r cold are the resistance ratios at the desired hot and cold trip points. note that these equations are linked. therefore, only one of the two trip points can be chosen, the other is determined by the default ratios designed in the ic. consider an example where a 60c hot trip point is desired. applications information
LTC3557/LTC3557-1 24 35571fc from the vishay curve 1 r-t characteristics, r hot is 0.2488 at 60c. using the above equation, r nom should be set to 46.4k. with this value of r nom , the cold trip point is about 16c. notice that the span is now 44c rather than the previous 40c. this is due to the decrease in temperature gain of the thermistor as absolute temperature increases. the upper and lower temperature trip points can be independently programmed by using an additional bias resistor as shown in figure 9. the following formulas can be used to compute the values of r nom and r1: r nom = r cold ?r hot 2.714 ?r25 r1 = 0.536 ? r nom ?r hot ?r25 for example, to set the trip points to 0c and 45c with a vishay curve 1 thermistor choose r nom = 3.266 ? 0.4368 2.714 ? 100k = 104.2k the nearest 1% value is 105k. r1 = 0.536 ? 105k C 0.4368 ? 100k = 12.6k the nearest 1% value is 12.7k. the ? nal solution is shown in figure 9 and results in an upper trip point of 45c and a lower trip point of 0c. battery charger stability considerations the LTC3557/LTC3557-1s battery charger contains both a constant voltage and a constant current control loop. the constant voltage loop is stable without any compensation when a battery is connected with low impedance leads. excessive lead length, however, may add enough series inductance to require a bypass capacitor of at least 1f from bat to gnd. furthermore, a 4.7f capacitor in series with a 0.2 to 1 resistor from bat to gnd is required to keep ripple voltage low when the battery is disconnected. high value, low esr multilayer ceramic chip capacitors reduce the constant voltage loop phase margin, possibly resulting in instability. ceramic capacitors up to 22f may be used in parallel with a battery, but larger ceramics should be decoupled with 0.2 to 1 of series resistance. in constant current mode, the prog pin is in the feedback loop rather than the battery voltage. because of the additional pole created by any prog pin capacitance, capacitance on this pin must be kept to a minimum. with applications information figure 8. typical ntc thermistor circuit figure 9. ntc thermistor circuit with additional bias resistor C + C + r nom 100k r ntc 100k ntc v ntc 18 0.017 ? v vntc ntc_enable 35571 f08 ntc block too_cold too_hot 0.765 ? v vntc 0.349 ? v vntc C + 19 C + C + r nom 105k r ntc 100k r1 12.7k ntc v ntc 18 0.017 ? v vntc ntc_enable 35571 f09 too_cold too_hot 0.765 ? v vntc 0.349 ? v vntc C + 19 ntc block
LTC3557/LTC3557-1 25 35571fc applications information no additional capacitance on the prog pin, the battery charger is stable with program resistor values as high as 25k. however, additional capacitance on this node reduces the maximum allowed program resistor. the pole frequency at the prog pin should be kept above 100khz. therefore, if the prog pin has a parasitic capacitance, c prog , the following equation should be used to calculate the maximum resistance value for r prog : r prog 1 2 ? 100khz ? c prog printed circuit board power dissipation considerations in order to be able to deliver maximum charge current under all conditions, it is critical that the exposed pad on the backside of the LTC3557/LTC3557-1 package is soldered to a ground plane on the board. correctly soldered to a 2500mm 2 ground plane on a double-sided 1oz copper board, the LTC3557/LTC3557-1 has a thermal resistance ( ja ) of approximately 37c/w. failure to make good thermal contact between the exposed pad on the backside of the package and an adequately sized ground plane will result in thermal resistances far greater than 37c/w. the conditions that cause the LTC3557/LTC3557-1 to reduce charge current due to the thermal protection feedback can be approximated by considering the power dissipated in the part. for high charge currents and a wall adapter applied to v out , the LTC3557/LTC3557-1 power dissipation is approximately: p d = (v out C bat) ? i bat + p d(sw1) + p d(sw2) + p d(sw3) where, p d is the total power dissipated, v out is the supply voltage, bat is the battery voltage and i bat is the battery charge current. p d(swx) is the power loss by the step-down switching regulators. the power loss for a step-down switching regulator can be calculated as follows: p d(swx) = (outx ? i out ) ? (100 C eff)/100 where outx is the programmed output voltage, i out is the load current and eff is the % ef? ciency which can be measured or looked up on an ef? ciency graph for the programmed output voltage. it is not necessary to perform any worst-case power dissipation scenarios because the LTC3557/LTC3557-1 will automatically reduce the charge current to maintain the die temperature at approximately 110c. however, the approximate ambient temperature at which the thermal feedback begins to protect the ic is: t a = 110c C p d ? ja example: consider the LTC3557/LTC3557-1 operating from a wall adapter with 5v (v out ) providing 1a (i bat ) to charge a li-ion battery at 3.3v (bat). also assume p d(sw1) = p d(sw2) = p d(sw3) = 0.05w, so the total power dissipation is: p d = (5v C 3.3v) ? 1a + 0.15w = 1.85w the ambient temperature above which the LTC3557/ LTC3557-1 will begin to reduce the 1a charge current, is approximately: t a = 110c C 1.85w ? 37c/w = 42c the LTC3557/LTC3557-1 can be used above 42c, but the charge current will be reduced below 1a. the charge current at a given ambient temperature can be approximated by: p d = 110 c?t a ja = v out ? bat () ?i bat + p d(sw1) + p d(sw 2) + p d(sw 3) thus: i bat = 110 c?t a ja ? p d(sw1) ?p d(sw 2) ?p d(sw 3) v out ? bat consider the above example with an ambient temperature of 55c. the charge current will be reduced to approximately: i bat = 110 c?55 c 37 c/w ? 0.15w 5v ? 3.3v = 1.49w ? 0.15w 1.7v = 786ma
LTC3557/LTC3557-1 26 35571fc if an external buck switching regulator controlled by the LTC3557/LTC3557-1 v c pin is used instead of a 5v wall adapter we see a signi? cant reduction in power dissipated by the LTC3557/LTC3557-1. this is because the external buck switching regulator will drive the powerpath output (v out ) to about 3.6v with the battery at 3.3v. if you go through the example above and substitute 3.6v for v out we see that thermal regulation does not kick in until about 93c. thus, the external regulator not only allows higher charging currents, but lower power dissipation means a cooler running application. printed circuit board layout considerations when laying out the printed circuit board, the following list should be followed to ensure proper operation of the LTC3557/LTC3557-1: 1. the exposed pad of the package (pin 29) should connect directly to a large ground plane to minimize thermal and electrical impedance. 2. the trace connecting the step-down switching regulator input supply pins (v in1 and v in2 ) and their respective decoupling capacitors should be kept as short as possible. the gnd side of these capacitors should connect directly to the ground plane of the part. these capacitors provide the ac current to the internal power mosfets and their drivers. its important to minimize inductance from these capacitors to the pins of the LTC3557/LTC3557-1. connect v in1 and v in2 to v out through a short low impedance trace. 3. the switching power traces connecting sw1, sw2 and sw3 to their respective inductors should be minimized to reduce radiated emi and parasitic coupling. due to the large voltage swing of the switching nodes, sensitive nodes such as the feedback nodes (fb1, fb2 and fb3) should be kept far away or shielded from the switching nodes or poor performance could result. 4. connections between the step-down switching regulator inductors and their respective output capacitors should be kept as short as possible. the gnd side of the output capacitors should connect directly to the thermal ground plane of the part. 5. keep the feedback pin traces (fb1, fb2 and fb3) as short as possible. minimize any parasitic capacitance between the feedback traces and any switching node (i.e., sw1, sw2, sw3 and logic signals). if necessary shield the feedback nodes with a gnd trace 6) connections between the LTC3557/LTC3557-1 power path pins (v bus and v out ) and their respective decoupling capacitors should be kept as short as pos- sible. the gnd side of these capacitors should connect directly to the ground plane of the part. v out should be decoupled with a 10f or greater ceramic capacitor as close as possible to the LTC3557/LTC3557-1. applications information
LTC3557/LTC3557-1 27 35571fc information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. typical application v in 68nf 10f 2.2f 2.2f 40.2k 4.7f 0.47f 22f 6.8h 3.3h 4.7h 4.7h optional high voltage buck input dfls240l hv in 8v to 38v (transients to 60v) 150k 499k 510 li-ion 3.3v 25ma always on 100k si2333ds si2333ds (opt) 2.1k boost 42 run/ss sw lt3480 gnd v c v c wall acpr v bus v out 5 r t 10 pg 11 9 26 10f 1f v out bat v out1 3.3v 600ma 3 24 clprog bv in1 27 2k 100k prog 20 v ntc ntc LTC3557/ LTC3557-1 18 19 ilim0 1 ilim1 2 en1 9 en2 10 en3 11 mode 8 100k ntc pmic control usb or 5v wall adapter 23 6 bv in2 16 chrg 28 gate 21 ldo3v3 4 sw1 5 fb1 7 bat 22 25 bd sync fb nc 7 nc 6 3 1 8 + 1.02m 324k 10pf 10f v out3 1.8v 400ma sw3 17 fb3 12 806k 649k 10pf 10f v out2 1.2v 400ma sw2 15 rst2 14 fb2 gnd 13 29 232k 100k rst2 464k 10pf 10f 35571 ta02
LTC3557/LTC3557-1 28 35571fc linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com ? linear technology corporation 2007 lt 0808 rev c ? printed in usa part number description comments power management ltc3455 dual dc/dc converter with usb power management and li-ion battery charger ef? ciency >96%, accurate usb current limiting (500ma/100ma), 4mm 4mm 24-pin qfn package ltc3456 2-cell multi-output dc/dc converter with usb power manager seamless transition between 2-cell battery, usb and ac wall adapter input power sources, qfn package ltc3555 switching usb power manager with li-ion/polymer charger, triple synchronous buck converter + ldo complete multifunction pmic: switch mode power manager and three buck regulators + ldo, charge current programmable up to 1.5a from wall adapter input, thermal regulation synchronous buck converters ef? ciency: >95%, adj outputs: 0.8v to 3.6v at 400ma/400ma/1a bat-track adaptive output control, 200m ideal diode, 4mm 5mm 28-pin qfn package ltc3559 linear usb li-ion/polymer battery charger with dual synchronous buck converter adjustable synchronous buck converters, ef? ciency: >90%, outputs: down to 0.8v at 400ma for each, charge current programmable up to 950ma, usb compatible, 3mm 3mm 16-pin qfn package battery chargers ltc4055 usb power controller and battery charger charges single cell li-ion batteries directly from a usb port, thermal regulation, 200m ideal diode, 4mm 4mm 16-pin qfn package ltc4066 usb power controller and li-ion battery charger with low loss ideal diode charges single cell li-ion batteries directly from a usb port, thermal regulation, 50m ideal diode, 4mm 4mm 24-pin qfn package ltc4085 usb power manager with ideal diode controller and li-ion charger charges single cell li-ion batteries directly from a usb port, thermal regulation, 200m ideal diode with <50m option, 4mm 3mm 14-pin dfn package ltc4088 high ef? ciency usb power manager and battery charger maximizes available power from usb port, bat-track, instant on operation, 1.5a max charge current, 180m ideal diode with <50m option, 3.3v/25ma always on ldo, 4mm 3mm 14-pin dfn package ltc4089/ltc4089-5 usb power manager with ideal diode controller and high ef? ciency li-ion battery charger 1.2a charger, 6v to 36v (40v max ), 200m ideal diode with 50m option, 6mm 3mm 22-pin dfn package related parts 4.00 p 0.10 (4 sides) s not a jedec package outline n ot to scale s ions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side, if present 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1 top mark (note 6) 0.40 p 0.05 28 27 1 2 bottom viewexposed pad 2.64 p 0.10 (4-sides) 0.75 p 0.05 r = 0.115 typ 0.20 p 0.05 0.40 bsc 0.200 ref 0.00 C 0.05 (uf28) qfn 0106 reva ded solder pad pitch and dimensions r mask to areas that are not soldered 0.70 p 0.05 0.20 p 0.05 0.40 bsc package outline pin 1 notch r = 0.20 typ or 0.35 s 45 o chamfer r = 0.05 typ package description uf package 28-lead plastic qfn (4mm 4mm) (reference ltc dwg # 05-08-1721 rev a)

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